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19 files changed

+1463
-1602
lines changed

Marlin/src/HAL/DUE/usb/genclk.h

Lines changed: 141 additions & 155 deletions
Original file line numberDiff line numberDiff line change
@@ -74,17 +74,17 @@ extern "C" {
7474
//@{
7575

7676
enum genclk_source {
77-
GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock
78-
GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock
79-
GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock
80-
GENCLK_PCK_SRC_MAINCK_4M_RC = 3, //!< Internal 4MHz RC oscillator as PCK source clock
81-
GENCLK_PCK_SRC_MAINCK_8M_RC = 4, //!< Internal 8MHz RC oscillator as PCK source clock
82-
GENCLK_PCK_SRC_MAINCK_12M_RC = 5, //!< Internal 12MHz RC oscillator as PCK source clock
83-
GENCLK_PCK_SRC_MAINCK_XTAL = 6, //!< External crystal oscillator as PCK source clock
84-
GENCLK_PCK_SRC_MAINCK_BYPASS = 7, //!< External bypass oscillator as PCK source clock
85-
GENCLK_PCK_SRC_PLLACK = 8, //!< Use PLLACK as PCK source clock
86-
GENCLK_PCK_SRC_PLLBCK = 9, //!< Use PLLBCK as PCK source clock
87-
GENCLK_PCK_SRC_MCK = 10, //!< Use Master Clk as PCK source clock
77+
GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock
78+
GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock
79+
GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock
80+
GENCLK_PCK_SRC_MAINCK_4M_RC = 3, //!< Internal 4MHz RC oscillator as PCK source clock
81+
GENCLK_PCK_SRC_MAINCK_8M_RC = 4, //!< Internal 8MHz RC oscillator as PCK source clock
82+
GENCLK_PCK_SRC_MAINCK_12M_RC = 5, //!< Internal 12MHz RC oscillator as PCK source clock
83+
GENCLK_PCK_SRC_MAINCK_XTAL = 6, //!< External crystal oscillator as PCK source clock
84+
GENCLK_PCK_SRC_MAINCK_BYPASS = 7, //!< External bypass oscillator as PCK source clock
85+
GENCLK_PCK_SRC_PLLACK = 8, //!< Use PLLACK as PCK source clock
86+
GENCLK_PCK_SRC_PLLBCK = 9, //!< Use PLLBCK as PCK source clock
87+
GENCLK_PCK_SRC_MCK = 10, //!< Use Master Clk as PCK source clock
8888
};
8989

9090
//@}
@@ -93,176 +93,162 @@ enum genclk_source {
9393
//@{
9494

9595
enum genclk_divider {
96-
GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1
97-
GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2
98-
GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4
99-
GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8
100-
GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16
101-
GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32
102-
GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64
96+
GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1
97+
GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2
98+
GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4
99+
GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8
100+
GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16
101+
GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32
102+
GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64
103103
};
104104

105105
//@}
106106

107107
struct genclk_config {
108-
uint32_t ctrl;
108+
uint32_t ctrl;
109109
};
110110

111-
static inline void genclk_config_defaults(struct genclk_config *p_cfg,
112-
uint32_t ul_id)
113-
{
114-
ul_id = ul_id;
115-
p_cfg->ctrl = 0;
111+
static inline void genclk_config_defaults(struct genclk_config *p_cfg, uint32_t ul_id) {
112+
ul_id = ul_id;
113+
p_cfg->ctrl = 0;
116114
}
117115

118-
static inline void genclk_config_read(struct genclk_config *p_cfg,
119-
uint32_t ul_id)
120-
{
121-
p_cfg->ctrl = PMC->PMC_PCK[ul_id];
116+
static inline void genclk_config_read(struct genclk_config *p_cfg, uint32_t ul_id) {
117+
p_cfg->ctrl = PMC->PMC_PCK[ul_id];
122118
}
123119

124-
static inline void genclk_config_write(const struct genclk_config *p_cfg,
125-
uint32_t ul_id)
126-
{
127-
PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
120+
static inline void genclk_config_write(const struct genclk_config *p_cfg, uint32_t ul_id) {
121+
PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
128122
}
129123

130124
//! \name Programmable Clock Source and Prescaler configuration
131125
//@{
132126

133-
static inline void genclk_config_set_source(struct genclk_config *p_cfg,
134-
enum genclk_source e_src)
135-
{
136-
p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);
137-
138-
switch (e_src) {
139-
case GENCLK_PCK_SRC_SLCK_RC:
140-
case GENCLK_PCK_SRC_SLCK_XTAL:
141-
case GENCLK_PCK_SRC_SLCK_BYPASS:
142-
p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK);
143-
break;
144-
145-
case GENCLK_PCK_SRC_MAINCK_4M_RC:
146-
case GENCLK_PCK_SRC_MAINCK_8M_RC:
147-
case GENCLK_PCK_SRC_MAINCK_12M_RC:
148-
case GENCLK_PCK_SRC_MAINCK_XTAL:
149-
case GENCLK_PCK_SRC_MAINCK_BYPASS:
150-
p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK);
151-
break;
152-
153-
case GENCLK_PCK_SRC_PLLACK:
154-
p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK);
155-
break;
156-
157-
case GENCLK_PCK_SRC_PLLBCK:
158-
p_cfg->ctrl |= (PMC_PCK_CSS_UPLL_CLK);
159-
break;
160-
161-
case GENCLK_PCK_SRC_MCK:
162-
p_cfg->ctrl |= (PMC_PCK_CSS_MCK);
163-
break;
164-
}
127+
static inline void genclk_config_set_source(struct genclk_config *p_cfg, enum genclk_source e_src) {
128+
p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);
129+
130+
switch (e_src) {
131+
case GENCLK_PCK_SRC_SLCK_RC:
132+
case GENCLK_PCK_SRC_SLCK_XTAL:
133+
case GENCLK_PCK_SRC_SLCK_BYPASS:
134+
p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK);
135+
break;
136+
137+
case GENCLK_PCK_SRC_MAINCK_4M_RC:
138+
case GENCLK_PCK_SRC_MAINCK_8M_RC:
139+
case GENCLK_PCK_SRC_MAINCK_12M_RC:
140+
case GENCLK_PCK_SRC_MAINCK_XTAL:
141+
case GENCLK_PCK_SRC_MAINCK_BYPASS:
142+
p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK);
143+
break;
144+
145+
case GENCLK_PCK_SRC_PLLACK:
146+
p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK);
147+
break;
148+
149+
case GENCLK_PCK_SRC_PLLBCK:
150+
p_cfg->ctrl |= (PMC_PCK_CSS_UPLL_CLK);
151+
break;
152+
153+
case GENCLK_PCK_SRC_MCK:
154+
p_cfg->ctrl |= (PMC_PCK_CSS_MCK);
155+
break;
156+
}
165157
}
166158

167-
static inline void genclk_config_set_divider(struct genclk_config *p_cfg,
168-
uint32_t e_divider)
169-
{
170-
p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;
171-
p_cfg->ctrl |= e_divider;
159+
static inline void genclk_config_set_divider(struct genclk_config *p_cfg, uint32_t e_divider) {
160+
p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;
161+
p_cfg->ctrl |= e_divider;
172162
}
173163

174164
//@}
175165

176-
static inline void genclk_enable(const struct genclk_config *p_cfg,
177-
uint32_t ul_id)
178-
{
179-
PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
180-
pmc_enable_pck(ul_id);
166+
static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id) {
167+
PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
168+
pmc_enable_pck(ul_id);
181169
}
182170

183-
static inline void genclk_disable(uint32_t ul_id)
184-
{
185-
pmc_disable_pck(ul_id);
171+
static inline void genclk_disable(uint32_t ul_id) {
172+
pmc_disable_pck(ul_id);
186173
}
187174

188-
static inline void genclk_enable_source(enum genclk_source e_src)
189-
{
190-
switch (e_src) {
191-
case GENCLK_PCK_SRC_SLCK_RC:
192-
if (!osc_is_ready(OSC_SLCK_32K_RC)) {
193-
osc_enable(OSC_SLCK_32K_RC);
194-
osc_wait_ready(OSC_SLCK_32K_RC);
195-
}
196-
break;
197-
198-
case GENCLK_PCK_SRC_SLCK_XTAL:
199-
if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {
200-
osc_enable(OSC_SLCK_32K_XTAL);
201-
osc_wait_ready(OSC_SLCK_32K_XTAL);
202-
}
203-
break;
204-
205-
case GENCLK_PCK_SRC_SLCK_BYPASS:
206-
if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {
207-
osc_enable(OSC_SLCK_32K_BYPASS);
208-
osc_wait_ready(OSC_SLCK_32K_BYPASS);
209-
}
210-
break;
211-
212-
case GENCLK_PCK_SRC_MAINCK_4M_RC:
213-
if (!osc_is_ready(OSC_MAINCK_4M_RC)) {
214-
osc_enable(OSC_MAINCK_4M_RC);
215-
osc_wait_ready(OSC_MAINCK_4M_RC);
216-
}
217-
break;
218-
219-
case GENCLK_PCK_SRC_MAINCK_8M_RC:
220-
if (!osc_is_ready(OSC_MAINCK_8M_RC)) {
221-
osc_enable(OSC_MAINCK_8M_RC);
222-
osc_wait_ready(OSC_MAINCK_8M_RC);
223-
}
224-
break;
225-
226-
case GENCLK_PCK_SRC_MAINCK_12M_RC:
227-
if (!osc_is_ready(OSC_MAINCK_12M_RC)) {
228-
osc_enable(OSC_MAINCK_12M_RC);
229-
osc_wait_ready(OSC_MAINCK_12M_RC);
230-
}
231-
break;
232-
233-
case GENCLK_PCK_SRC_MAINCK_XTAL:
234-
if (!osc_is_ready(OSC_MAINCK_XTAL)) {
235-
osc_enable(OSC_MAINCK_XTAL);
236-
osc_wait_ready(OSC_MAINCK_XTAL);
237-
}
238-
break;
239-
240-
case GENCLK_PCK_SRC_MAINCK_BYPASS:
241-
if (!osc_is_ready(OSC_MAINCK_BYPASS)) {
242-
osc_enable(OSC_MAINCK_BYPASS);
243-
osc_wait_ready(OSC_MAINCK_BYPASS);
244-
}
245-
break;
246-
247-
#ifdef CONFIG_PLL0_SOURCE
248-
case GENCLK_PCK_SRC_PLLACK:
249-
pll_enable_config_defaults(0);
250-
break;
251-
#endif
252-
253-
#ifdef CONFIG_PLL1_SOURCE
254-
case GENCLK_PCK_SRC_PLLBCK:
255-
pll_enable_config_defaults(1);
256-
break;
257-
#endif
258-
259-
case GENCLK_PCK_SRC_MCK:
260-
break;
261-
262-
default:
263-
Assert(false);
264-
break;
265-
}
175+
static inline void genclk_enable_source(enum genclk_source e_src) {
176+
switch (e_src) {
177+
case GENCLK_PCK_SRC_SLCK_RC:
178+
if (!osc_is_ready(OSC_SLCK_32K_RC)) {
179+
osc_enable(OSC_SLCK_32K_RC);
180+
osc_wait_ready(OSC_SLCK_32K_RC);
181+
}
182+
break;
183+
184+
case GENCLK_PCK_SRC_SLCK_XTAL:
185+
if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {
186+
osc_enable(OSC_SLCK_32K_XTAL);
187+
osc_wait_ready(OSC_SLCK_32K_XTAL);
188+
}
189+
break;
190+
191+
case GENCLK_PCK_SRC_SLCK_BYPASS:
192+
if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {
193+
osc_enable(OSC_SLCK_32K_BYPASS);
194+
osc_wait_ready(OSC_SLCK_32K_BYPASS);
195+
}
196+
break;
197+
198+
case GENCLK_PCK_SRC_MAINCK_4M_RC:
199+
if (!osc_is_ready(OSC_MAINCK_4M_RC)) {
200+
osc_enable(OSC_MAINCK_4M_RC);
201+
osc_wait_ready(OSC_MAINCK_4M_RC);
202+
}
203+
break;
204+
205+
case GENCLK_PCK_SRC_MAINCK_8M_RC:
206+
if (!osc_is_ready(OSC_MAINCK_8M_RC)) {
207+
osc_enable(OSC_MAINCK_8M_RC);
208+
osc_wait_ready(OSC_MAINCK_8M_RC);
209+
}
210+
break;
211+
212+
case GENCLK_PCK_SRC_MAINCK_12M_RC:
213+
if (!osc_is_ready(OSC_MAINCK_12M_RC)) {
214+
osc_enable(OSC_MAINCK_12M_RC);
215+
osc_wait_ready(OSC_MAINCK_12M_RC);
216+
}
217+
break;
218+
219+
case GENCLK_PCK_SRC_MAINCK_XTAL:
220+
if (!osc_is_ready(OSC_MAINCK_XTAL)) {
221+
osc_enable(OSC_MAINCK_XTAL);
222+
osc_wait_ready(OSC_MAINCK_XTAL);
223+
}
224+
break;
225+
226+
case GENCLK_PCK_SRC_MAINCK_BYPASS:
227+
if (!osc_is_ready(OSC_MAINCK_BYPASS)) {
228+
osc_enable(OSC_MAINCK_BYPASS);
229+
osc_wait_ready(OSC_MAINCK_BYPASS);
230+
}
231+
break;
232+
233+
#ifdef CONFIG_PLL0_SOURCE
234+
case GENCLK_PCK_SRC_PLLACK:
235+
pll_enable_config_defaults(0);
236+
break;
237+
#endif
238+
239+
#ifdef CONFIG_PLL1_SOURCE
240+
case GENCLK_PCK_SRC_PLLBCK:
241+
pll_enable_config_defaults(1);
242+
break;
243+
#endif
244+
245+
case GENCLK_PCK_SRC_MCK:
246+
break;
247+
248+
default:
249+
Assert(false);
250+
break;
251+
}
266252
}
267253

268254
//! @}

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