75
75
#define HEIGHT 64
76
76
#define PAGE_HEIGHT 8
77
77
78
- uint8_t u8g_WriteEscSeqP_2_wire (u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_seq);
78
+ #define CMD_COL_ADR (N ) (0x10 | ((N) >> 4 )), ((N) & 0xF )
79
+ #define CMD_PAGE_ADR (N ) (0x20 ), (N)
80
+ #define CMD_COLUMN_RANGE (N,O ) (0x21 ), (N), (O)
81
+ #define CMD_PAGE_RANGE (N,O ) (0x22 ), (N), (O)
82
+ #define CMD_SCROLL (N ) ((N) ? 0x2F : 0x2E )
83
+ #define CMD_START_LINE (N ) (0x40 | (N))
84
+ #define CMD_CONTRAST (N ) (0x81 ), (N)
85
+ #define CMD_CHARGE_PUMP (N ) (0x8D ), ((N) ? 0x14 : 0x10 )
86
+ #define CMD_ADC_REVERSE (N ) ((N) ? 0xA1 : 0xA0 )
87
+ #define CMD_ALL_PIX (N ) ((N) ? 0xA5 : 0xA4 )
88
+ #define CMD_INVERTED (N ) ((N) ? 0xA7 : 0xA6 )
89
+ #define CMD_MUX_RATIO (N ) (0xA8 ), (N)
90
+ #define CMD_ON (N ) ((N) ? 0xAF : 0xAE )
91
+ #define CMD_OUT_MODE (N ) ((N) ? 0xC8 : 0xC0 )
92
+ #define CMD_DISP_OFFS (N ) (0xD3 ), (N)
93
+ #define CMD_OSC_FREQ (R,F ) (0xD5 ), ((F) << 4 | (R))
94
+ #define CMD_CHARGE_PER (P,D ) (0xD9 ), ((D) << 4 | (P))
95
+ #define CMD_COM_CONFIG (N ) (0xDA ), ((N) ? 0x12 : 0x02 )
96
+ #define CMD_VCOM_DESEL (N ) (0xDB ), (N)
97
+ #define CMD_NOOP () (0xE3 )
79
98
80
- // SH1106 (132x64) is compatible with SSD1306 (128x64) by adding a small margin to the larger display
99
+ uint8_t u8g_WriteEscSeqP_2_wire ( u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_seq);
81
100
82
- #define SH1106_PAGE_ADR (N ) (0x20 ), (N)
83
- #define SH1106_COL_ADR (N ) (0x10 | ((N) >> 4 )), ((N) & 0xFF )
84
- #define SH1106_COLUMN_RANGE (N,O ) (0x21 ), (N), (O)
85
- #define SH1106_PAGE_RANGE (N,O ) (0x22 ), (N), (O)
86
- #define SH1106_SCROLL (N ) ((N) ? 0x2F : 0x2E )
87
- #define SH1106_START_LINE (N ) (0x40 | (N))
88
- #define SH1106_CONTRAST (N ) (0x81 ), (N)
89
- #define SH1106_CHARGE_PUMP (N ) (0x8D ), ((N) ? 0x14 : 0x10 )
90
- #define SH1106_ADC_REVERSE (N ) ((N) ? 0xA1 : 0xA0 )
91
- #define SH1106_ALL_PIX (N ) ((N) ? 0xA5 : 0xA4 )
92
- #define SH1106_INVERTED (N ) ((N) ? 0xA7 : 0xA6 )
93
- #define SH1106_MUX_RATIO (N ) (0xA8 ), (N)
94
- #define SH1106_ON (N ) ((N) ? 0xAF : 0xAE )
95
- #define SH1106_OUT_MODE (N ) ((N) ? 0xC8 : 0xC0 )
96
- #define SH1106_DISP_OFFS (N ) (0xD3 ), (N)
97
- #define SH1106_OSC_FREQ (R,F ) (0xD5 ), ((F) << 4 | (R))
98
- #define SH1106_CHARGE_PER (P,D ) (0xD9 ), ((D) << 4 | (P))
99
- #define SH1106_COM_CONFIG (N ) (0xDA ), ((N) ? 0x12 : 0x02 )
100
- #define SH1106_VCOM_DESEL (N ) (0xDB ), (N)
101
- #define SH1106_NOOP () (0xE3 )
101
+ // SH1106 is compatible with SSD1306, but is 132x64. Display 128x64 centered within the 132x64.
102
102
103
103
static const uint8_t u8g_dev_sh1106_128x64_data_start_2_wire[] PROGMEM = {
104
- SH1106_COL_ADR (2 ), // Column 2 to center 128 pixels in 132 pixels
105
- U8G_ESC_END // End of sequence
104
+ CMD_COL_ADR (2 ), // Column 2 to center 128 pixels in 132 pixels
105
+ U8G_ESC_END // End of sequence
106
106
};
107
107
108
108
static const uint8_t u8g_dev_sh1106_128x64_init_seq_2_wire[] PROGMEM = {
109
- U8G_ESC_ADR (0 ), // Initiate command mode
110
- SH1106_ON (0 ), // Display off, sleep mode
111
- SH1106_MUX_RATIO (0x3F ), // Mux ratio
112
- SH1106_DISP_OFFS (0 ), // Display offset
113
- SH1106_START_LINE (0 ), // Start line
114
- SH1106_ADC_REVERSE (1 ), // Segment remap A0/A1
115
- SH1106_OUT_MODE (1 ), // 0: scan dir normal, 1: reverse
116
- SH1106_COM_CONFIG (1 ), // COM pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5)
117
- SH1106_CONTRAST (0xCF ), // Set contrast control
118
- SH1106_PAGE_ADR (0x02 ), // page addressing mode
119
- SH1106_COLUMN_RANGE (2 , 129 ), // Set column range 2 .. 129
120
- SH1106_PAGE_RANGE (0 , 7 ), // Set page range 0 .. 7
121
- SH1106_CHARGE_PER (0x1 , 0xF ), // Pre-charge period
122
- SH1106_VCOM_DESEL (0x40 ), // Vcomh deselect level
123
- SH1106_ALL_PIX (0 ), // Output RAM to display
124
- SH1106_INVERTED (0 ), // Normal display mode
125
- SH1106_OSC_FREQ (0 , 8 ), // Clock divide ratio (0:1) and oscillator frequency (8)
126
- SH1106_CHARGE_PUMP (1 ), // Charge pump setting
127
- SH1106_SCROLL (0 ), // Deactivate scroll
128
- SH1106_ON (1 ), // Display on
129
- U8G_ESC_END // End of sequence
109
+ U8G_ESC_ADR (0 ), // Initiate command mode
110
+ CMD_ON (0 ), // Display off, sleep mode
111
+ CMD_MUX_RATIO (0x3F ), // Mux ratio
112
+ CMD_DISP_OFFS (0 ), // Display offset
113
+ CMD_START_LINE (0 ), // Start line
114
+ CMD_ADC_REVERSE (1 ), // Segment remap A0/A1
115
+ CMD_OUT_MODE (1 ), // 0: scan dir normal, 1: reverse
116
+ CMD_COM_CONFIG (1 ), // COM pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5)
117
+ CMD_CONTRAST (0xCF ), // Set contrast control
118
+ CMD_PAGE_ADR (0x02 ), // page addressing mode
119
+ CMD_COLUMN_RANGE (2 , 129 ), // Set column range 2 .. 129
120
+ CMD_PAGE_RANGE (0 , 7 ), // Set page range 0 .. 7
121
+ CMD_CHARGE_PER (0x1 , 0xF ), // Pre-charge period
122
+ CMD_VCOM_DESEL (0x40 ), // Vcomh deselect level
123
+ CMD_ALL_PIX (0 ), // Output RAM to display
124
+ CMD_INVERTED (0 ), // Normal display mode
125
+ CMD_OSC_FREQ (0 , 8 ), // Clock divide ratio (0:1) and oscillator frequency (8)
126
+ CMD_CHARGE_PUMP (1 ), // Charge pump setting
127
+ CMD_SCROLL (0 ), // Deactivate scroll
128
+ CMD_ON (1 ), // Display ON
129
+ U8G_ESC_END // End of sequence
130
130
};
131
131
132
132
uint8_t u8g_dev_sh1106_128x64_2x_2_wire_fn (u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
@@ -142,7 +142,7 @@ uint8_t u8g_dev_sh1106_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t m
142
142
u8g_WriteEscSeqP_2_wire (u8g, dev, u8g_dev_sh1106_128x64_data_start_2_wire);
143
143
u8g_WriteByte (u8g, dev, 0xB0 | (pb->p .page *2 )); // Select current page
144
144
u8g_SetAddress (u8g, dev, 1 ); // Data mode
145
- u8g_WriteSequence (u8g, dev, pb->width , (uint8_t *) pb->buf );
145
+ u8g_WriteSequence (u8g, dev, pb->width , (uint8_t *)pb->buf );
146
146
u8g_SetChipSelect (u8g, dev, 0 );
147
147
u8g_SetAddress (u8g, dev, 0 ); // Instruction mode
148
148
u8g_WriteEscSeqP_2_wire (u8g, dev, u8g_dev_sh1106_128x64_data_start_2_wire);
@@ -157,39 +157,39 @@ uint8_t u8g_dev_sh1106_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t m
157
157
return u8g_dev_pb16v1_base_fn (u8g, dev, msg, arg);
158
158
}
159
159
160
- uint8_t u8g_dev_sh1106_128x64_2x_i2c_2_wire_buf[WIDTH* 2 ] U8G_NOCOMMON ;
161
- u8g_pb_t u8g_dev_sh1106_128x64_2x_i2c_2_wire_pb = { {16 , HEIGHT, 0 , 0 , 0 }, WIDTH, u8g_dev_sh1106_128x64_2x_i2c_2_wire_buf};
160
+ uint8_t u8g_dev_sh1106_128x64_2x_i2c_2_wire_buf[WIDTH * 2 ] U8G_NOCOMMON;
161
+ u8g_pb_t u8g_dev_sh1106_128x64_2x_i2c_2_wire_pb = { { 16 , HEIGHT, 0 , 0 , 0 }, WIDTH, u8g_dev_sh1106_128x64_2x_i2c_2_wire_buf };
162
162
u8g_dev_t u8g_dev_sh1106_128x64_2x_i2c_2_wire = { u8g_dev_sh1106_128x64_2x_2_wire_fn, &u8g_dev_sh1106_128x64_2x_i2c_2_wire_pb, U8G_COM_SSD_I2C_HAL };
163
163
164
164
// ///////////////////////////////////////////////////////////////////////////////////////////
165
165
166
166
static const uint8_t u8g_dev_ssd1306_128x64_data_start_2_wire[] PROGMEM = {
167
- SH1106_COL_ADR (0 ), // Column 0
168
- U8G_ESC_END // End of sequence
167
+ CMD_COL_ADR (0 ), // Column 0
168
+ U8G_ESC_END // End of sequence
169
169
};
170
170
171
171
static const uint8_t u8g_dev_ssd1306_128x64_init_seq_2_wire[] PROGMEM = {
172
- U8G_ESC_CS (0 ), // Disable chip
173
- SH1106_ON (0 ), // Display off , sleep mode
174
- SH1106_MUX_RATIO (0x3F ), // Mux ratio
175
- SH1106_DISP_OFFS (0 ), // Display offset
176
- SH1106_START_LINE (0 ), // Start line
177
- SH1106_ADC_REVERSE (1 ), // Segment remap A0/A1
178
- SH1106_OUT_MODE (1 ), // 0: scan dir normal, 1: reverse
179
- SH1106_COM_CONFIG (1 ), // COM pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5)
180
- SH1106_CONTRAST (0xCF ), // Set contrast control
181
- SH1106_PAGE_ADR ( 0x02 ), // page addressing mode
182
- SH1106_COLUMN_RANGE (0 , 127 ), // Set column range 0 .. 127
183
- SH1106_PAGE_RANGE (0 , 7 ), // Set page range from 0 .. 7
184
- SH1106_CHARGE_PER (0x1 , 0xF ), // Pre-charge period
185
- SH1106_VCOM_DESEL (0x40 ), // Vcomh deselect level
186
- SH1106_ALL_PIX (0 ), // Send RAM to display
187
- SH1106_INVERTED (0 ), // Normal display mode
188
- SH1106_OSC_FREQ (0 , 8 ), // Clock divide ratio (0:1) and oscillator frequency (8)
189
- SH1106_CHARGE_PUMP (1 ), // Charge pump setting
190
- SH1106_SCROLL (0 ), // Deactivate scroll
191
- SH1106_ON (1 ), // Display on
192
- U8G_ESC_END // End of sequence
172
+ U8G_ESC_CS (0 ), // Disable chip
173
+ CMD_ON (0 ), // Display OFF , sleep mode
174
+ CMD_MUX_RATIO (0x3F ), // Mux ratio
175
+ CMD_DISP_OFFS (0 ), // Display offset
176
+ CMD_START_LINE (0 ), // Start line
177
+ CMD_ADC_REVERSE (1 ), // Segment remap A0/A1
178
+ CMD_OUT_MODE (1 ), // 0: scan dir normal, 1: reverse
179
+ CMD_COM_CONFIG (1 ), // COM pin HW config, sequential COM pin config (bit 4), disable left/right remap (bit 5)
180
+ CMD_CONTRAST (0xCF ), // Set contrast control
181
+ CMD_PAGE_ADR ( 2 ), // Page addressing mode
182
+ CMD_COLUMN_RANGE (0 , 127 ), // Set column range 0 .. 127
183
+ CMD_PAGE_RANGE (0 , 7 ), // Set page range from 0 .. 7
184
+ CMD_CHARGE_PER (0x1 , 0xF ), // Pre-charge period
185
+ CMD_VCOM_DESEL (0x40 ), // Vcomh deselect level
186
+ CMD_ALL_PIX (0 ), // Send RAM to display
187
+ CMD_INVERTED (0 ), // Normal display mode
188
+ CMD_OSC_FREQ (0 , 8 ), // Clock divide ratio (0:1) and oscillator frequency (8)
189
+ CMD_CHARGE_PUMP (1 ), // Charge pump setting
190
+ CMD_SCROLL (0 ), // Deactivate scroll
191
+ CMD_ON (1 ), // Display ON
192
+ U8G_ESC_END // End of sequence
193
193
};
194
194
195
195
uint8_t u8g_dev_ssd1306_128x64_2x_2_wire_fn (u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
@@ -205,7 +205,7 @@ uint8_t u8g_dev_ssd1306_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t
205
205
u8g_WriteEscSeqP_2_wire (u8g, dev, u8g_dev_ssd1306_128x64_data_start_2_wire);
206
206
u8g_WriteByte (u8g, dev, 0xB0 | (pb->p .page *2 )); // Select current page
207
207
u8g_SetAddress (u8g, dev, 1 ); // Data mode
208
- u8g_WriteSequence (u8g, dev, pb->width , (uint8_t *) pb->buf );
208
+ u8g_WriteSequence (u8g, dev, pb->width , (uint8_t *)pb->buf );
209
209
u8g_SetChipSelect (u8g, dev, 0 );
210
210
u8g_SetAddress (u8g, dev, 0 ); // Instruction mode
211
211
u8g_WriteEscSeqP_2_wire (u8g, dev, u8g_dev_ssd1306_128x64_data_start_2_wire);
@@ -220,8 +220,8 @@ uint8_t u8g_dev_ssd1306_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t
220
220
return u8g_dev_pb16v1_base_fn (u8g, dev, msg, arg);
221
221
}
222
222
223
- uint8_t u8g_dev_ssd1306_128x64_2x_i2c_2_wire_buf[WIDTH* 2 ] U8G_NOCOMMON ;
224
- u8g_pb_t u8g_dev_ssd1306_128x64_2x_i2c_2_wire_pb = { {16 , HEIGHT, 0 , 0 , 0 }, WIDTH, u8g_dev_ssd1306_128x64_2x_i2c_2_wire_buf};
223
+ uint8_t u8g_dev_ssd1306_128x64_2x_i2c_2_wire_buf[WIDTH * 2 ] U8G_NOCOMMON;
224
+ u8g_pb_t u8g_dev_ssd1306_128x64_2x_i2c_2_wire_pb = { {16 , HEIGHT, 0 , 0 , 0 }, WIDTH, u8g_dev_ssd1306_128x64_2x_i2c_2_wire_buf };
225
225
u8g_dev_t u8g_dev_ssd1306_128x64_2x_i2c_2_wire = { u8g_dev_ssd1306_128x64_2x_2_wire_fn, &u8g_dev_ssd1306_128x64_2x_i2c_2_wire_pb, U8G_COM_SSD_I2C_HAL };
226
226
227
227
// ///////////////////////////////////////////////////////////////////////////////////////////
@@ -236,7 +236,7 @@ uint8_t u8g_WriteEscSeqP_2_wire(u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_s
236
236
for (;;) {
237
237
uint8_t value = u8g_pgm_read (esc_seq);
238
238
if (is_escape == 0 ) {
239
- if (value != 255 ) {
239
+ if (value != 0xFF ) {
240
240
if (u8g_WriteByte (u8g, dev, value) == 0 ) return 0 ;
241
241
if (u8g_WriteByte (u8g, dev, I2C_CMD_MODE) == 0 ) return 0 ;
242
242
}
@@ -245,17 +245,17 @@ uint8_t u8g_WriteEscSeqP_2_wire(u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_s
245
245
}
246
246
}
247
247
else {
248
- if (value == 255 ) {
248
+ if (value == 0xFF ) {
249
249
if (u8g_WriteByte (u8g, dev, value) == 0 ) return 0 ;
250
250
if (u8g_WriteByte (u8g, dev, I2C_CMD_MODE) == 0 ) return 0 ;
251
251
}
252
- else if (value == 254 ) {
252
+ else if (value == 0xFE ) {
253
253
break ;
254
254
}
255
255
else if (value >= 0xF0 ) {
256
- // not yet used, do nothing
256
+ // Not yet used, do nothing
257
257
}
258
- else if (value >= 0xE0 ) {
258
+ else if (value >= 0xE0 ) {
259
259
u8g_SetAddress (u8g, dev, value & 0x0F );
260
260
}
261
261
else if (value >= 0xD0 ) {
@@ -270,11 +270,10 @@ uint8_t u8g_WriteEscSeqP_2_wire(u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_s
270
270
u8g_SetResetHigh (u8g, dev);
271
271
u8g_Delay (value);
272
272
}
273
- else if (value >= 0xBE ) {
274
- // not yet implemented
273
+ else if (value >= 0xBE ) { // Not yet implemented
275
274
// u8g_SetVCC(u8g, dev, value & 0x01);
276
275
}
277
- else if (value <= 127 ) {
276
+ else if (value <= 0x7F ) {
278
277
u8g_Delay (value);
279
278
}
280
279
is_escape = 0 ;
0 commit comments