ggml-cuda : restore prop.integrated on HIP builds

[liminfei-amd]

PR #16308 sets info.devices[id].integrated = false unconditionally for every
CUDA/HIP device — a workaround for corrupted output on Jetson Orin (#15034). On
HIP/ROCm this discards the device's real hipDeviceProp_t.integrated flag.

With the cached integrated field forced to false, supports_buft() refuses
CUDA host buffers on AMD APU/UMA parts, even though get_type() already reads
prop.integrated directly (#23007). The two paths therefore disagree, breaking
host-buffer use on integrated GPUs under ROCm.

This guards the workaround to non-HIP (CUDA) builds and restores
prop.integrated for HIP, so the Jetson workaround stays in place for CUDA while
AMD APUs report their true integrated status:

#if defined(GGML_USE_HIP)
        info.devices[id].integrated = prop.integrated;
#else
        info.devices[id].integrated = false; // Temporarily disabled ... (#15034)
#endif

Validated on an AMD Ryzen AI MAX+ 395 (gfx1151 APU, ROCm 7.2.1): the HIP device
now reports integrated=1 and the cached info.devices[id].integrated matches
prop.integrated. Discrete AMD GPUs report integrated=0 and are unaffected.

Fixes #23977

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This is an experimental, AI-generated code change, reviewed by AMD engineers before submission.

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[liminfei-amd]

Thanks for the review and for the AI-usage policy reminder.

Disclosure: I used an AI assistant to help draft the patch and this description, but the change is a minimal, human-directed fix that I fully understand and can maintain. Below is a line-by-line explanation and the hardware evidence behind it.

Background

ggml_cuda_init() caches per-device properties. PR #16308 set info.devices[id].integrated = false unconditionally for all CUDA/HIP devices as a workaround for corrupted output on Jetson Orin (#15034). That cached flag is later read by ggml_backend_cuda_buffer_type_supports_buft() to decide whether CUDA host buffers may be used. On AMD HIP/ROCm the real device flag hipDeviceProp_t.integrated is meaningful (APUs are truly integrated/UMA), and another path already reads prop.integrated directly (#23007). So on an AMD APU the two paths disagree: one believes the device is discrete, the other integrated, which breaks host-buffer use on integrated GPUs.

The change, line by line

#if defined(GGML_USE_HIP)
        info.devices[id].integrated = prop.integrated;
#else
        info.devices[id].integrated = false; // Temporarily disabled due to issues with corrupted output (e.g. #15034)
#endif

• #if defined(GGML_USE_HIP) — compile-time guard; GGML_USE_HIP is defined only for HIP/ROCm builds, so this splits the behavior by backend with no runtime cost.
• info.devices[id].integrated = prop.integrated; — for HIP builds, store the device's actual integrated flag. prop is the hipDeviceProp_t already queried a few lines above (used for prop.totalGlobalMem). This makes the cached field consistent with the prop.integrated reads elsewhere.
• #else and the original = false; line — unchanged for non-HIP (CUDA) builds, so the Jetson Orin workaround from Eval bug: Broken/no Gemma 3n output on CUDA (Nvidia Jetson Orin Nano) #15034 stays exactly as-is for CUDA.
• #endif — closes the guard.

Net effect: discrete AMD GPUs report prop.integrated == 0 (no behavior change), AMD APUs report 1 (fixed), and CUDA is untouched.

Hardware validation

Reproduced and verified on an AMD Ryzen AI MAX+ 395 (gfx1151, RDNA3.5 APU) running ROCm 7.2.1:

• A small HIP probe calling hipGetDeviceProperties reports integrated=1 for this APU.
• With the stock code, info.devices[id].integrated stays 0 (inconsistent with prop.integrated); with this patch the cached value matches prop.integrated (1), so the host-buffer support check and the UMA path agree.
• A discrete RDNA4 GPU (gfx1201) reports integrated=0 and is unaffected, confirming the change is scoped to genuinely-integrated parts.

Happy to adjust the wording if preferred — I can explain any part of the change in more detail.

[0cc4m]

This came up in a different discussion, it's still valid, right?

[JohannesGaessler]

(Already several weeks ago) I had an off-site discussion with NVIDIA engineers regarding UMA in reaction to this PR. In the course of the discussion it became clear that getting the memory coherence right is non-trivial but one them said they "will work on it". However, nothing else came of it. If according to AMD engineers the program logic as it is being changed in this PR is correct for AMD hardware then my opinion is that we can just merge it since they very likely know better than me.

[liminfei-amd]

Thanks @0cc4m for reopening this, and thanks @JohannesGaessler for the review and the NVIDIA context.

Yes, this is still valid for HIP. We revalidated it on a gfx1151 APU: the ROCm backend changes from rejecting ROCm_Host to supporting it, and a real model run uses ROCm_Host output/compute buffers successfully.

Short generation tests with both CPU-heavy and full-HIP offload completed normally, with no measurable performance regression.

[imrehg]

Judging by the influx of issue reports that are traced back to this change, it might not have been correctly validated update.