Layered SystemVerilog testbench for verifying a parameterized Synchronous FIFO. Includes directed and constrained-random tests, functional coverage, assertions, and scoreboard-based checking.
Exercícios desenvolvidos durante a disciplina Concepção Estruturada de Circuitos Integrados, relacionando os mais diversos assuntos da mesma.
Add a description, image, and links to the cadence-xcelium topic page so that developers can more easily learn about it.
To associate your repository with the cadence-xcelium topic, visit your repo's landing page and select "manage topics."