A resource-conscious neural network implementation for MCUs
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Updated
Apr 22, 2025 - C++
A resource-conscious neural network implementation for MCUs
Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) QSPI Flash | 4-stage pipeline
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