xilinx-vivado

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Here are 65 public repositories matching this topic...

Domipheus / ArtyS7-RPU-SoC

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Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

c fpga firmware vhdl riscv spi vivado apache2 hdmi fpga-soc risc-v xilinx-vivado dvid riscv32

Updated Oct 5, 2020
VHDL

muhammadaldacher / FPGA-Design-of-a-Digital-Analog-Clock-Display-using-Digilent-Basys3-Artix-7

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The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga display. Picoblaze processor is used to control the Analog & Digital displays of the clock.

fpga vhdl verilog assembly-language digital-design xilinx-vivado picoblaze-processor

Updated Mar 17, 2019
VHDL

shinde-shantanu / FPGA_TDC

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Time to Digital Converter on an FPGA

fpga verilog xilinx-vivado nexys4ddr

Updated Oct 8, 2020
VHDL

Yourigh / Rotary-encoder-VHDL-design

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VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.

zynq encoder vivado xilinx-fpga zybo zynq-7010 xilinx-vivado rotary axi

Updated Mar 24, 2017
VHDL

Wissance / 2DImageProcessing

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2d Images processing system with FPGA (Zynq 7k) from two dragster linescanner (DR-2k-7)

Updated Sep 15, 2017
VHDL

Wissance / ImageCaptureSystem

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A Xilinx IP Core and App for line scanner image capture and store

image video computer-vision scanner spi capture-the-flag xilinx-fpga dragster linescanners cmosis awaiba two-channel-image-capture-system axi-vdma axi-quad-spi video-ip-core xilinx-vivado dr-2k-7 xilinx-axi-vdma xilinx-ip

Updated Sep 5, 2017
VHDL

simoneruffini / NORM

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Framework for emulation of non volatile memory using off-the-shelf FPGAs

fpga vhdl non-volatile-memory xilinx-fpga openhardware xilinx-vivado feram

Updated Sep 9, 2021
VHDL

luminoso / cr-countones

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Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs

fpga finite-state-machine xilinx vivado xilinx-fpga xilinx-vivado nexys4ddr

Updated Aug 30, 2017
VHDL

SnrNotHere16 / HDMIBreakout

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A ZYNQ 7020 project that plays breakout via HDMI.

game sdk fpga arcade verilog gpio-pins hdmi breakout-game fpga-soc interrupt vga xilinx-fpga xilinx-vivado system-on-chip zynq-7000 block-design zybo-z7 hdmi-out ps-pl-communication

Updated Apr 13, 2022
VHDL

mcagriaksoy / DegreeAdjustableRadar

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Zynq ZedBoard SoC Lecture Final Project, degree adjustable ultrasonic sensor application

c zynq vhdl embedded-systems xilinx ultrasonic-sensor pwm zedboard xilinx-fpga pwm-driver xilinx-vivado ultrasonic-sensor-distance pwm-servo-driver

Updated May 13, 2019
VHDL

Injabie3 / dj-board

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SFU - ENSC 452 (Advanced Digital System Design) Term Project: The Ultimate DJ Board using a Zedboard. Also mirrored on SFU CSIL's GitLab.

c vhdl embedded-systems xilinx zedboard xilinx-vivado simon-fraser-university xilinx-sdk

Updated Nov 29, 2018
VHDL

SnrNotHere16 / FPGADivisionFloatingPoint

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A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)

c sdk fpga zynq verilog xilinx floating-point hdl division xilinx-vivado microblaze zynq-7000 nexys4ddr floating-ip artix-7 floating-point-conversion

Updated Apr 5, 2022
VHDL

Kampi / TinyAVR

Sponsor

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VHDL design of an AVR8 CPU.

avr cpu fpga vhdl xilinx mcu xilinx-fpga xilinx-vivado

Updated Jan 19, 2022
VHDL

vinayak1998 / Reflex-Tester

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This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.

fpga architecture vhdl xilinx vivado xilinx-fpga xilinx-ise basys3 lfsr xilinx-vivado hand-eye-coordination

Updated Nov 29, 2017
VHDL

lucarinelli / computer_architecture_project

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Our project material for the Computer Architecture course for Computer Engineering students at Politecnico di Torino (Polytechnic University of Turin)

fpga polito vhdl xilinx hdmi computer-architecture xilinx-fpga xilinx-vivado politecnico-di-torino